[Lity]

Ok. Here it is.

Vendor 1106, Device 3189. DDR266 SDRAM.

Register 64, bit 6 represents RAS Active Time (tRAS)

This shows the BIOS & PCR Profile of WPCREDIT for KT400:
0=TRAS 5T
1=TRAS 6T

This shows the Everest:
0=TRAS 6T
1=TRAS 7T

I think the BIOS & PCR Profile tells correct value, and Everest is wrong.

This post has been edited by Lity: 06 November 2009 - 11:49 PM

[Fiery]

Do you have a KT400 or KT400A chipset? What motherboard do you have?

[Lity]

MB = Canyon CN-7V4A
North bridge = VIA VT8377 Apollo KT400
MB ID = 08/27/2003-KT400-8235-6A6LYD4BC-00

OEM = DFI AD77

[Lity]

I forgot. MemSet shows the same thing that the BIOS and PCR Profile (from George Breese) for WPCREDIT too.

[Fiery]

VIA's KT400 datasheet (Revision 1.1 - January 13, 2003) confirms EVEREST is right:

0=TRAS 6T
1=TRAS 7T


Regards,
Fiery

[Lity]

As I understand the role of values of registers varies depending on the frequency of the memory bus.
So,
at a frequency < 400 Mhz:
0 = TRAS 5T
1 = TRAS 6T

at frequency = 400 Mhz:

0 = TRAS 6T
1 = TRAS 7T

In support I giving shots of BIOS on display screen.


Unfortunately I can't verify that.

[Fiery]

KT400 chipset doesn't support DDR400 memory.

[Lity]

Fiery, on 18 November 2009 - 12:10 AM, said:

KT400 chipset doesn't support DDR400 memory.

How this is possible? It's a KT400.
Support is visible even in the name of the chipset.
And how then to explain the presence in the BIOS 400 MHz frequency option? And this option works, and not just for beauty.

This is really strange.
By the way, KT400 and KT400A differ in hardware or software?

[Fiery]

KT400 datasheet says the chipset supports up to DDR333 memory frequencies. KT400A adds DDR400 support. You may want to check the relevant Wiki page as well:

http://en.wikipedia....ki/VIA_chipsets

The BIOS Setup entry may just be there because of possible overclocking headroom.

[Lity]

Ok, thanks. Now I see. A swindle of a century))

But how can that be that all the other timings may have minimum values 2-2-2 and only tRAS have a minimum value equal to 6, when possible minimum is 5? It looks like a misunderstanding.

[Fiery]

Lity, on 17 November 2009 - 11:22 PM, said:

But how can that be that all the other timings may have minimum values 2-2-2 and only tRAS have a minimum value equal to 6, when possible minimum is 5? It looks like a misunderstanding.

I'm sorry, but you gotta ask VIA about their chipset registers We're not hardware developers, but software developers here at Lavalys

[Lity]

Fiery, on 20 November 2009 - 08:58 PM, said:

We're not hardware developers, but software developers here at Lavalys

Yeah, i know that

This post has been edited by Lity: 20 November 2009 - 08:18 PM